1. Field of the Invention
This invention relates generally to the field of integrated circuit packaging.
2. Description of the Related Art
Laminated constructions of relatively fine pitch circuit layers and power planes are used in many integrated circuit packaging applications. Typically, features in relatively fine pitch circuit layers are much finer than features in power planes. Interconnections between relatively fine pitch circuit layers and attendant power planes are typically done by mechanically drilling through the construction after the relatively fine pitch circuit layers and power planes have been laminated together, and then filling the drilled hole with conductive material to make a via. In this approach, the tolerance of the mechanical drilling process and lamination lay-up must be accommodated on all layers of the laminated construction. This method requires relatively large capture pads and/or keep-out zones on all relatively fine pitch circuit layers in the construction at the target drill location, to ensure that the drilled hole interconnects with the capture pad. A large capture pad is highly undesirable in many circuit packaging applications where power distribution to and from the power planes at precise locations on the relatively fine pitch circuit layers is required. For example, present circuit technology can produce 25 micron lines and spaces on high density relatively fine pitch circuit layers. However, mechanical methods of lay-up, lamination, drilling, etc., often require 300 to 600 microns of tolerance build-up at the interconnect locations. The capture pads must accommodate not only a large drill hole, but also account for tolerance build-up due to drill wander, misregistration of the relatively fine pitch circuit layers and power planes, and thermal and mechanical dimensional instability of the materials, especially during high temperature and pressure lamination. These large capture pads in the circuit design add significant electrical parasitics (inductance, resistance and capacitance) to the design, which can significantly degrade the electrical performance of the design. These electrical parasitics can be quite deleterious to the package performance because currents in excess of 50 amps can be switched at sub-nanosecond speeds and extremely low inductances are required to minimize the noise associated with this current switching activity.
Others have recognized the problem of tolerance build-up in the laminate structure. A widely practiced method for addressing this problem is to use more sophisticated and precise methods of drilling interconnects, such as laser drilling coupled with precision optical benches or stages. Laser drilling is typically used in situations where precision is required in the interconnection between power planes and relatively fine pitch circuit layers. However, this method is still subject to the dimensional instability of the dielectric materials, lamination lay-up tolerances, and the positioning of the laser with respect to the fine pitch circuit features. Also, these methods are significantly more expensive than mechanical drilling and merely provide a smaller drilled hole in the laminate structure to form the interconnect, but do not address the intrinsic tolerance build-up inherent in the lamination lay-up, registration, material dimensional instability, etc. Thus, the laser drilling technique results in much more expensive laminate structures and only minimizes a portion of the total tolerance build-up.
In another approach to the problem of precision interconnection of a relatively fine pitch circuit trace to an outer conductive layer or power plane, sequential processing has been proposed to ameliorate much of the tolerance build-up in the laminate structure. However, sequential processing requires that each layer be formed on the previous layer. In brief, this approach leads to yield degradation because the yield of the final structure is the cumulative yield of each individual layer. In advanced circuit design, the yield of each layer may be low; therefore, the cumulative yield of multiple layers may be impractically low. The cost of this type of processing, therefore, is also high.